The present invention relates to a linear amplifier; and, more particularly, to an automatically gain controllable linear differential amplifier using a variable degeneration resistor.
A linear integrated circuit (IC), a typical analog IC can have output signals, which is varying continuously, in proportion to an input signal level. The linear integrated circuit, theoretically, can generate unlimited numbers of variety states of the signal.
A linear amplifier can be described linear input to output relation, which is linear transfer function. The linear amplifier for a low frequency input is commonly used for an audio amplifier and a linear amplifier for a high frequency input is commonly used for various transceiver systems.
Typically, the linear amplifier for a high frequency input signal requires high gain but linearity is not much important when the input signal is low, however, when the input signal is high, the linear amplifier for a low frequency input signal requires reasonable gain but linearity is very important.
In case the linear amplifier is used for a communication transceiver, if the linear amplifier has non-linearity with high frequency input, then output signals may be distorted and receiving sensitivity may be decreased by the harmonics. The receiving sensitivity may also be decreased when an amplifying gain of the linear amplifier is too small.
The harmonics are generated due to an internal trans conductance value of a Metal Oxide Semiconductor (MOS) transistor which has the non-linear characteristic in the linear amplifier having transistors. Also, the harmonics are induced by connecting a collector and an emitter at a base in a bipolar transistor.
The bipolar transistor is composed of two diodes coupled each other and has a non-linear characteristic of an output current according to an input voltage.
An output signal of an active element including a MOS transistor and an Operational Amplifier (OP-AMP) can be expressed by an equation as follow:
xcexdo=xcex11.xcexdi+xcex12.xcexdi2+xcex13.xcexdi3+ . . . xe2x80x83xe2x80x83Eq.(1) 
where, xcexdo represents an output signal and xcexdi represents an input signal and xcex11, xcex12 and xcex13 are coefficients defining the linearity of active elements. Ideal active elements have xe2x80x9c0xe2x80x9d as the coefficients xcex12 and xcex13 so an output signal of the ideal active elements is a value simply scaled by xcex11. However, active elements generally have some value for coefficients xcex12 and xcex13 thus the active elements have a non-linearity by coefficients xcex12 and xcex13. The coefficient xcex12 defines a quantity of a non-linearity of the quadratic term and the coefficient xcex13 defines a quantity of the non-linearity of a cubic term.
Higher terms of Eq.(1) xcex12.xcexdi2+xcexd3.xcexdi3 is a signal having similar frequency to an input signal by the non-linearity of the active elements and it causes inter-modulating the signal with the input signal. As a result, an un-wanted output signal is generated. Inhere, an Input referred 3rd-order Intercept Point (IIP3) is a input power with a unit xe2x80x9cdBmxe2x80x9d when a power of the harmonics generated by third term of Eq. (1) xcex13.xcexdi becomes identical to the input signal. If the current of input signal is lower than the IIP3, then the active elements amplify the harmonics more than the input signal. Therefore, a signal/noise ratio (S/N) will be worse. In other words, the IPP3 can be used as a reference for determining the linearity of the amplifier.
Referring to Eq. (1), the value of the higher term of the equation 1 xcex12.xcexdi2+xcex13.xcexdi3 is increasing rapidly comparing to the input signal so the harmonics is will be increasing rapidly too. Therefore, the harmonics needs to be controlled and decreased effectively. If the harmonics cannot be controlled, the harmonics will be increased by the higher terms of Eq. (1) more than the input signal so the noise will be amplified more than the input signal.
Therefore, the transceiver system, which generates the harmonics, needs an amplifier that can control the gain of the amplifier according to a value of the signal and has the enhanced linear characteristics when the gain is so small.
FIG. 1 is a circuit diagram of a conventional linear differential amplifier.
Referring to FIG. 1, the conventional linear differential amplifier includes loads 10 and 11, bias current sources 40 and 41, NMOS transistors 20, 21 and degeneration resistor 30. The loads 10 and 11 are provided between an applied power VDD and an output end Voutxe2x88x92 and between the applied power VDD and an output end Vout+. The load can be a resistor, a capacitor or an inductor. The load also can be an alternate resistor, which is a mixture of a capacitor and an inductor. The bias current sources 40 and 41 are connected to a ground. The NMOS transistor 20 is connected between the bias current source 40 and output end Voutxe2x88x92 and the NMOS transistor 21 is connected between the bias current source 41 and the output end Vout+. The NMOS transistors have differential input signal V+ and Vxe2x88x92 as inputs of their gates. An end of the degeneration resistors are connected at a connection point between the bias power source 40 and another end of the NMOS transistor 20 and a connection point between the bias power source 41 and the NMOS transistor 21. The degeneration resistor can be implemented as variety form, however, in an integration process of a conventional CMOS processing, a polysilicon-resistor is used for the degeneration resistors because of characteristics of the polysilicon-resistor such as an excellent linearity and small a parasitic capacitance.
Operations of the conventional linear differential amplifier will be described below in detail.
When the differential input signal V+ and Vxe2x88x92 is not applied to gates of the NMOS transistors 20 and 21, currents of I1 and I2 have identical value IB1(=IB2) by the bias current sources 40 and 41.
In a meantime, if the differential input signal V+ has a higher electric potential level than the differential input signal Vxe2x88x92, an electric potential level of the negative output end Voutxe2x88x92 is higher than an electric potential level of the positive output end Vout+ by a current difference between two loads 10 and 11.
If the degeneration resistor 30 is connected to the NMOS transistors 20 and 21, then a virtual ground is formed and the harmonics, which has the linearity among signals flowed at the NMOS transistors 20 and 21, are cancelled each other. Therefore, the linearity of the linear differential amplifier will be improved. Inhere, the harmonics IIP3 is outputted from the NMOS transistors 20 and 21 by an amplified signal of the differential input signal V+ and Vxe2x88x92 and non-linearity of the NMOS transistors 20 and 21. At this point, phase of the differential input signal V+ and Vxe2x88x92 are reversed but the harmonics generated by the non-linearity of the NMOS transistors 20 and 21 has variety phases. Therefore, the linearity of the amplifier is improved by canceling a part of the harmonics, which is generated in response to the different input signal V+ and Vxe2x88x92.
However, the above-mentioned conventional linear differential amplifier using the degeneration resistor 30 has a fixed resistor value thus the gain cannot be controlled and there is a limitation for improving the linearity when the electric potential level of the differential input signal is higher. Also, it is very difficult to integrate the degeneration resistor using the polysilicon-resistor in a CMOS process.
FIG. 2 is a circuit diagram of another conventional linear differential amplifier.
Referring to FIG. 2, the conventional linear differential amplifier has the same structure except a NMOS transistor 50 used instead of the degeneration resistor 30 in FIG. 1.
By using the NMOS transistor 50 as a resistor, the conventional linear differential amplifier in FIG. 2 improves the problem of the conventional linear differential amplifier in FIG. 1, which is difficulty of the integration of the polisilicon degeneration resistor in the CMOS process. If a constant voltage VB is applied to the gate of the NMOS transistor 50 then the NMOS transistor 50 will be operated as a resistor.
However, a resistor value of the NMOS transistor 50 is not stable when the electric potential level of the differential input signals V+ and Vxe2x88x92 are increasing. If the electric potential level of the differential input signals V+ and Vxe2x88x92 are increased, then a current outputted from source/drain ends of the NMOS transistor 50 is increased too. At this point, since the gate voltage VB has a steady value, the value of the differential input signal V+ and Vxe2x88x92 will be increased. Therefore, the value of the NMOS transistor 50 will be unstable according to increasing the value of the differential input signals V+ and Vxe2x88x92. Since the differential input signals V+ and Vxe2x88x92 are changed, the value of the IIP3 is not improved. Additionally, the linearity of the amplifier becomes worse by the non-linearity of the NMOS transistor 50. The non-linearity of the NMOS transistor causes the value of the differential input signals V+ and Vxe2x88x92 larger. The large value of the differential input signals V+ and Vxe2x88x92 will cause the linearity of the amplifier worse.
FIG. 3 is a circuit diagram of another conventional linear differential amplifier.
Referring to FIG. 3, the conventional linear differential amplifier uses two transistors 60 and 61 instead of the NMOS transistor 50 in the FIG. 2. Sources and drains of the two NMOS transistors 60 and 61 are connected each other so that the source of one transistor is connected to the drain of the other. The two NMOS transistors 60 and 61 are controlled by an input signal V+ and input signal Vxe2x88x92 as a gate input.
Referring to FIG. 3, the conventional linear differential amplifier improves an unstable resistor value of the NMOS transistor 50, which is a problem of the conventional linear differential amplifier in FIG. 2. The NMOS transistors 60 and 61 maintains a stable resistor value in spite of alternating the potential level of the differential input signal V+ and Vxe2x88x92 since the NMOS transistors 60 and 61 use the differential input signal V+ and Vxe2x88x92 as the gate voltage. In other words, if the potential level of the differential input signal V+ is increased and the differential input signal Vxe2x88x92 is decreased then the resistor value of the NMOS transistor 60 will be decreased and the resistor value of the NMOS transistor 61 will be increased. The two NMOS transistors 60 and 61 are connected in parallel so the resistor value can be maintained at a certain level.
However, the above-mentioned conventional linear differential amplifiers in FIGS. 1, 2 and 3 cannot control an amplifying gain, therefore, the IIP3 can not be improved when the potential level of the differential input signal is alternated.
It is, therefore, an object of the present invention to provide a linear differential amplifier for minimizing nonlinearity of harmonics and controlling an amplifying gain.
In accordance with an aspect of the present invention, there is provided the linear differential amplifier including: input unit for receiving a positive input signal and a negative input signal; a bias current source connected to one end of the input unit, for providing a bias current; load unit connected to another end of the input unit, for providing an output level difference between a positive output unit and a negative output unit corresponding to the positive input signal an the negative input signal; a first MOS transistor coupled between the bias current source and the input unit, having the positive input signal as a gate input and using a gain control signal as a circuit board bias voltage; and a second MOS transistor coupled between the bias current source and the input unit, having the negative input signal as a gate input and using the gain control signal as a circuit board bias voltage.